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S E M I C O N D U C T O R, I N C .
Figure 1. Block Diagram
FBIN
11
TQ1090
S1
10
REFCLK S0
9 8
GND
7
GND
6
GND
5
TEST 12 VDD 13
Phase Detector VCO
4 VDD 3 2
Q10 Q9
11-Output Configurable Clock Buffer
Features
Q0
14
GND 15 Q1 Q2
16 17
MUX Divide Logic /2 Output Buffers Group C Group A Group B
1 GND 28 27
S1 S0
Q8 Q7
VDD 18
26 VDD
* Wide frequency range: 33 MHz to 45 MHz 65 MHz to 90 MHz and 130 MHz to 180 MHz * Output configurations: four outputs at fREF four outputs at 2x fREF two output at 4x fREF or five outputs at 1/2 x fREF three outputs at fREF two outputs at 2x fREF * Selectable Phase Shift: -2t, -t, 0, +t (t = 1/fvco) * Low output-to-output skew: 150 ps (max) within a group * Near-zero propagation delay -350 ps 500 ps (max) or -350 ps 700 ps (max) * TTL-compatible I/O with 30 mA output drive * Ideal for Power PCTM designs * 28-pin J-lead surface-mount package
SYSTEM TIMING PRODUCTS
19
20
21
22
23
24
25
GND
Q3
Q4
VDD
Q5
Q6
GND
TriQuint's TQ1090 is a configurable clock buffer which generates 11 outputs, operating over a wide range of frequencies from 33 MHz to 45MHz, 65 MHz to 90 MHz and 130 MHz to 180 MHz. The outputs are available at 1x, 2x and 4x, or at 1/2x, 1x and 2x, or at 1/4 x, 1/2 x and 1x the reference clock frequency, fREF. When one of the Group A outputs (Q0-Q4) is used as feedback to the PLL, all Group A outputs will be at fREF, all Group B outputs (Q5-Q8) will be at 2x fREF and all Group C outputs (Q9,Q10) will be at 4x fREF. When one of the Group B outputs is used as feedback to the PLL, all Group A outputs will be at 1/2 x fREF, all Group B outputs will be at fREF and all Group C outputs will be at 2x fREF. When one of the Group C outputs is used as feedback to the PLL, all Group A outputs will be at 1/4 x fREF, all Group B outputs will be at 1/2 x fREF and all Group C outputs will be at fREF. A very stable internal Phase-Locked Loop (PLL) provides low-jitter operation. This completely self-contained PLL requires no external capacitors or resistors. The PLL's Voltage-Controlled Oscillator (VCO) has a frequency range from 260 MHz to 360 MHz. By feeding back one of the output clocks to FBIN, the PLL continuously maintains frequency and phase synchronization between the reference clock (REFCLK) and each of the outputs.
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1
TQ1090
The phase relationship of the Group A outputs to Group B and C are controlled by the phase-select pins S0 and S1. The phase difference can be varied from -2t, -t, 0 or +t, where t = 1/fvco. TriQuint's patented output buffer design delivers a very low output-to-output skew of 150 ps (max). The TQ1090's symmetrical TTL outputs are capable of sourcing and sinking 30 mA.
The Shift Select pins, S0 and S1, control the phase shift of the Group A outputs (Q0 - Q4), relative to the other outputs. The user can select from four incremental phase shifts as shown in Table 2 (Phase Selection). The phase shift increment (t) is calculated using the following equation, where n is the divide mode: t=
1
(f REF) (n)
Functional Description
The core of the TQ1090 is a Phase-Locked Loop (PLL) that continuously compares the reference clock (REFCLK) to the feedback clock (FBIN), maintaining a zero frequency difference between the two. Since one of the outputs is always connected to FBIN, the PLL keeps the propagation delay between the outputs and the reference clock within -350 ps +500 ps for the TQ1090-MC500, and within -350 ps +700 ps for the TQ1090-MC700. The internal Voltage-Controlled Oscillator (VCO), has an operating range of 260 MHz to 360 MHz, as shown in Table 1. The combination of the VCO and the Divide Logic enables the TQ1090 to operate between 33 MHz and 45 MHz, 65 MHz and 90 MHz, and from 130 MHz to 180 MHz. In the test mode, the PLL is bypassed and REFCLK is connected directly to the Divide Logic block via the MUX, as shown in Figure 1. This mode is useful for debug and test purposes. The test mode is outlined in Table 3. The maximum rise and fall time at the output pins is 1.4 ns. All outputs of the TQ1090 are TTL-compatible with 30 mA symmetric drive and a minimum VOH of 2.4 V.
Power-Up/Reset Synchronization
After power-up or reset, the PLL requires time before it achieves synchronization lock. The maximum time required for synchronization (TSYNC) is 500 ms.
Table 1. Frequency Mode Selection
Output Feedback
Group A Group B Group C
Test
0 0 0
Mode
/8 /4 /2
Reference Clock Frequency Range
35 MHz - 45 MHz 65 MHz - 90 MHz 130 MHz - 180 MHz
Group A: Q0-Q4
35 MHz - 45 MHz 35 MHz - 45 MHz 35 MHz - 45 MHz
Output Frequency Range Group B: Q5,Q08 Group c: Q9,Q10
65 MHz - 90 MHz 65 MHz - 90 MHz 65 MHz - 90 MHz 130 MHz - 180 MHz 130 MHz - 180 MHz 130 MHz - 180 MHz
2
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TQ1090
Table 2. Phase Shift Selection
S0
0 1 0 1
S1
0 0 1 1
Phase Shift (Group A: Q0 - Q4)
+t 0 -t -2t
Table 2. Test Mode Selection
Test
1
Mode
/2
Ref. Clock
fREF
Group A Outputs Q0-Q4
fREF / 8
Group B Outputs Q5-Q18
fREF / 4
Group C Outputs Q9-Q10
fREF / 2
Layout Guidelines
Multiple ground and power pins on the TQ1090 reduce ground bounce. Good layout techniques, however, are necessary to guarantee proper operation and to meet the specifications across the full operating range. We recommend bypassing each of the VDD supply pins to the nearest ground pin, as close to the chip as possible. Figure 2 shows the recommended power layout for the TQ1090. The bypass capacitors should be located on the same side of the board as the TQ1090. The VDD traces connect to an inner-layer VDD plane. All of the ground pins (GND) are connected to a small ground plane on the surface beneath the chip. Multiple through-holes connect this small surface plane to an inner-layer ground plane. The capacitors (C1-C5) are 0.1 mF. TriQuint's test board uses X7R temperaturestable capacitors in 1206 SMD cases.
Figure 2. Top Layer Layout of Power Pins (approx. 3.3x)
V DD C4
Pin 1
V DD
SYSTEM TIMING PRODUCTS
C3
Ground Plane
V DD C2
Pin 15
C5 V DD V DD
C1
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3
TQ1090
Absolute Maximum Ratings 1
Storage temperature Ambient temperature with power applied2 Supply voltage to ground potential DC input voltage DC input current Package thermal resistance (MQuad) Die junction temperature -65 C to +150 C -55 C to +100 C -0.5 V to +7.0 V -0.5 V to +(VDD + 0.5)V -30 mA to +5 mA JA = 45 C/W TJ = 150 C
DC Characteristics (VDD = +5 V + 5%, TA = 0 C to +70 C) 3
Limits 4 Typ
3.4 4.1 0.27 2.0 0.8 -156 0 2 119 IIN = -18 mA -0.70 -400 25 1000 170 -1.2 0.5
Symbol
VOHT VOHC VOL VIH 5 VIL5 IIL IIH II IDDS 6 VI
Description
Output HIGH voltage Output HIGH voltage Output LOW voltage Input HIGH level Input LOW level Input LOW current Input HIGH current Input HIGH current Power supply current Input clamp voltage
Test Conditions
VDD = Min IOH= -30 mA VIN= VIH or VIL VDD = Min IOH= -1 mA VIN= VIH or VIL VDD = Min IOL = 30 mA VIN= VIH or VIL Guaranteed input logical HIGH Voltage for all Inputs Guaranteed input logical LOW Voltage for all inputs VDD = Max VDD = Max VDD = Max VDD = Max VDD = Min VIN = 0.40 V VIN = 2.7 V VIN = 5.5 V
Min
2.4 3.2
Max
Unit
V V V V V A A A mA V
Capacitance
Symbol
CIN 3
Description
Input capacitance
Test Conditions
VIN = 2.0 V at f = 1 MHz
Min
Typ
6
Max
Unit
pF
Notes:
1. Exceeding these parameters may damage the device. 2. Maximum ambient temperature with device not switching and unloaded. 3. These values apply to both TQ1089-MC500 and TQ1089-MC700. 4. Typical limits are at VDD = 5.0 V and TA = 25 C. 5. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 6. This parameter is measured with device not switching and unloaded. 7. These parameters are not 100% tested, but are periodically sampled.
4
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TQ1090
AC Characteristics (VDD = +5 V + 5%, TA = 0 C to +70 C)
Symbol
t CPWH t CPWL t IR
Input Clock (REFCLK)
CLK pulse width HIGH CLK pulse width LOW Input rise time (0.8 V - 2.0V)
Test Conditions (Figure 3) 1
Figure 4 Figure 4
Min
2 2 --
Typ
------
Max Unit
-- -- 2.0 ns ns ns
Symbol
t OR,t OF t PD1 2 t PD2 2 t SKEW1 3 t SKEW2 3 t SKEW3 3 t SKEW4 t CYC 4 t JP 5 t JR 5 t SYNC 6
3
Output Clocks (Q0-Q10)
Rise/fall time (0.8 V - 2.0V) CLK to FBIN (TQ1090-MC500) CLK to FBIN (TQ1090-MC700) Rise-rise, fall-fall (within group) Rise-rise, fall-fall (group-to-group, aligned) Rise-fall, fall-rise Duty-cycle Variation Period-to-Period Jitter Random Jitter Synchronization Time
Test Conditions (Figure 3) 1
Figure 4 Figure 4 Figure 4 Figure 5 Figure 6 (skew2 takes into account skew1) (skew4 takes into account skew3) Figure 4 Figure 4 Figure 4
Min
350 -850 -1050 -- -- -- -- -1000 -- -- --
Typ
-- -350 -350 60 75 -- -- 0 80 190 10
Max Unit
1400 +150 +350 150 350 650 1200 +1000 200 400 500 ps ps ps ps ps ps ps ps ps ps s
Rise-rise, fall-fall (group-to-group, non-aligned) (skew3 takes into account skews1, 2)
Notes: 1. All measurements are tested with a REFCLK having a rise time of 0.5 ns (0.8 V to 2.0 V). 2. The PLL maintains alignment of CLK and FBIN at all times. This specification applies to the rising edge only because the input duty cycle can vary while the output duty cycle is typically 50/50. The delay tPD is measured at the 1.5 V level between CLK and FBIN. 3. Skew specifies the width of the window in which outputs switch, and is measured at 1.5 V. Skew 1 is a subset of skew 2. Skew 2 is a subset of skew 3. Skew 3 is a subset of skew 4. Definition of skew terms: Rise-rise: Skew between rising edges (low to high transitions). Fall-fall: Skew between falling edges (high to low transitions). Rise-fall, fall-rise: Skew between rising-to-falling and falling-to-rising edges. Within a group: Skew between outputs of the same group (for example, skew among Group A outputs) Group-to-group: Skew between outputs of any group (for example, skew between Group A to Group B outputs) Aligned: Skew between outputs that are in phase. Non-aligned: Skew between outputs that are not in phase. 4. This specification represents the deviation from 50/50 on the outputs. 5. Jitter specifications refer to peak-to-peak value. tJR is the jitter on the output with respect to the reference clock. tJP is the jitter on the output with respect to the same output's previous rising edge. 6. tSYNC is the time required for the PLL to synchronize; this assumes the presence of a CLK signal and a connection from one of the outputs to FBIN.
Figure 3. AC Test Circuit
+5 V R1 R2 Z FBIN
Y 50 X Q0 Q1 Q2 * * * * Q10
+5 V R1 R2 +5 V R1 R2 +5 V R1 R2
+5 V R1 R2 Notes: R1 = 160 R2 = 71 Y+Z=X Z CLK
* * * *
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5
SYSTEM TIMING PRODUCTS
TQ1090
Switching Waveforms
Figure 4. General Timing
Figure 5. tSKEW1
Figure 6. tSKEW2
6
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TQ1090
28-Pin MQuad J-Leaded Package Mechanical Specification
(All dimensions in inches)
.172 .005 .490 .005 .045 X 45 .445 .005 .132 .005 .040 MIN
PIN 1 8 0.125 VENT PLUG 15 .015 X 45 22
.490 .005 .445 .005 .445 .028 .005 .018
.410 .015
.050 TYP. .060
.050 TYP. NON-ACCUM.
.104 .005
28-Pin MQuad Pin Description
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Pin Name
GND Q9 Q10 VDD GND GND GND GND REFCLK GND FBIN TEST VDD Q0
Description
Ground Output Clock 9 (C1) Output Clock 10 (C2) +5 V Ground Ground Ground Ground Reference Clock Ground Feedback In Test +5 V Output Clock 0 (A1)
I/O
-- O O -- -- -- -- -- I -- I I -- O
Pin #
15 16 17 18 19 20 21 22 23 24 25 26 27 28
Pin Name
GND Q1 Q2 VDD GND Q3 Q4 VDD Q5 Q6 GND VDD Q7 Q8
Description
Ground Output Clock 1 (A2) Output Clock 2 (A3) +5 V Ground Output Clock 3 (A4) Output Clock 4 (A5) +5 V Output Clock 5 (B1) Output Clock 6 (B2) Ground +5 V Output Clock 7 (B3) Output Clock 8 (B4)
I/O
-- O O -- -- O O -- O O -- -- O O
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7
SYSTEM TIMING PRODUCTS
TQ1090
Output Characteristics
The IV characteristics, transition times, package characteristics, device and bond wire characteristics for the TQ1090 are describedin Tables 4 through 9 and Figures 9 through 11. These output characteristics are provided for modelling purposes only. TriQuint does not guarantee the information in these tables and figures.
Figure 9. IOH vs.VOH
HIGH
0 -20 -40 0.0 1.0 2.0 3.0 4.0 5.0
VOH min VOH max
Figure 10. IOL vs.VOL
LOW
160 140 120
VOL min VOL max
IOH (mA)
-60 -80 -100 -120 -140 -160
IOL (mA)
100 80 60 40 20 0
Volts
0.0
1.0
2.0
3.0
4.0
5.0
Volts
Table 4. IOH vs.VOH
VOH
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
Table 5. IOL vs.VOL
IOH min (mA)
-70 -70 -68 -65 -59 -48 -29 0 0 0 0 40 90 115 135 145
IOH max (mA)
-160 -157 -152 -142 -130 -106 -79 -42 0 0 0 120 265 350 410 435
VOL
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 10.0
IOL min (mA)
-145 -135 -115 -90 -40 0 37 49 53 54 54 54 54 54 54 54 54
IOL max (mA)
-435 -410 -350 -265 -120 0 97 140 155 157 159 160 160 160 160 160 160
Notes: 1. These are worst-case corners for process, voltage, and temperature. 2. Includes diode to ground current.
8
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TQ1090
Table 6. Above-VDD and Below-Ground Characteristics
Table 9. Rise and Fall Times (Into 0 pF, 50 Ohms to 1.5 V)
Diode to GND V I (mA)
0.0 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 -2.0 -2.5 -3.0 0 0 0 -5 -15 -35 -55 -75 -300 -350 -360
Diode Stack to VDD V I (mA)
5.0 5.4 5.5 5.6 5.7 5.8 5.9 6.0 7.0 7.5 8.0 0 0 0 5 15 35 55 75 300 350 360
Time (ns) TR min (V) TR max (V)
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 0.15 0.15 0.16 0.18 0.23 0.26 0.34 0.46 0.67 0.89 1.12 1.32 1.50 1.73 1.93 2.15 2.75 2.58 2.75 2.90 3.02 3.12 3.17 3.19 3.20 3.20 3.20 3.20 3.20 3.20 3.20 3.20 3.20 3.20 3.20 3.20 0.32 0.32 0.32 0.32 0.32 0.32 0.32 0.34 0.39 0.49 0.63 0.86 1.09 1.27 1.45 1.64 2.23 2.00 2.23 2.41 2.50 2.64 2.77 2.86 2.95 2.99 3.02 3.02 3.04 3.04 3.04 3.04 3.04 3.04 3.04 3.04
TF min (V) TF max (V)
3.20 3.20 3.06 2.86 2.62 2.38 2.17 2.00 1.85 1.69 1.52 1.38 1.26 1.12 0.96 0.83 0.52 0.61 0.52 0.45 0.39 0.33 0.29 0.24 0.21 0.19 0.17 0.16 0.16 0.15 0.15 0.15 0.15 0.15 0.15 0.15 3.04 3.04 2.95 2.90 2.68 2.50 2.36 2.22 2.09 1.95 1.86 1.68 1.59 1.49 1.36 1.23 0.95 1.00 0.95 0.86 0.77 0.73 0.68 0.64 0.59 0.55 0.53 0.50 0.45 0.41 0.40 0.37 0.36 0.32 0.32 0.91
Note:
TriQuint does not guarantee diode operation for purposes other than ESD protection.
Figure 11. Output Model
L1 DIE C1 C2 L2 OUTPUT
1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
Table 7. Device and Bond Wire Characteristics (Estimated)
L1
2 nH
C1
10 pF
Table 8. 28-Pin MQuad Package Characteristics
L2
1.85 nH
3.1 3.2 3.3 3.4 3.5
C2
0.40 pF
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9
SYSTEM TIMING PRODUCTS
TQ1090
Ordering Information
To order, please specify as shown below:
TQ1090-MC nnn
11-Output Configurable Clock Buffer
Propagation delay skew:
500 -350 ps 500 ps 700 -350 ps 700 ps
Note: All parts are marked as MC500. MC700 parts have a "2" added to the marking.
Temperature range: 0 C to 70 C (Commercial) Package: MQuad
Additional Information
For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: sales@tqs.com Tel: (503) 615-9000 Fax: (503) 615-8900
For technical questions and additional information on specific applications: Email: applications@tqs.com
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright (c) 1997 TriQuint Semiconductor, Inc. All rights reserved. Revision 1.1.A November 1997
10
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